This invention relates to a semiconductor integrated circuit that comprises a plurality of interconnection layers and to a method of designing such a semiconductor integrated circuit. The present invention pertains in particular to achieving a reduction of the area occupied by interconnection lines in order to increase the level of integration of the semiconductor integrated circuit.
With the rapid improvement in the level of semiconductor integrated circuit integration, reduction in interconnection line area and increase in high electric current density are problems the semiconductor industry will have to face in the near future. In recent years, various approaches, for example, to interconnection line materials with high electromigration (hereinafter referred to as "EM") resistance, new semiconductor device structures, and layout design techniques allowing for the EM resistance have been proposed, have been made.
As an interconnection line material, a copper- or titanium-added aluminum alloy is currently used for semiconductor integrated circuits. A structure (called the "plug structure") is adopted, more specifically tungsten (W) is filled into a contact hole or into a via hole by means of an LPCVD (low-pressure chemical vapor deposition) process for establishing electrical continuity between interconnection lines of vertically disposed interconnection layers constructed of an aluminum alloy.
Various layout design techniques have been proposed. Japanese patent applications, which have been laid open under publication nos. 3-289155 and 4-107953, respectively, each disclose a layout design technique in which the waveforms and values of electric currents which flow in individual interconnection lines are extracted by arithmetic operations for reflection on the layout.
The fact that the EM depends upon the current density, upon the interconnection line width, and upon the current waveform has been known to exist (see "The Enhancement of Electromigration Lifetime under High Frequency Pulsed Conditions," IEICE Trans. Fundamentals, Vol. E77-A, No. 1, p.195, 1994 by K. Hiraoka and others). Additionally, faulty mode, in which voids are produced due to electromigration in an aluminum alloy overlying a plug structure of tungsten, has lately attracted considerable attention (see "The Effect of Copper Concentration on the Electromigration Lifetime of Layered Aluminum-Copper (Ti--AlCu--Ti) Metallurgy with Tungsten Diffusion Barriers," Proc. of IEEE, VMIC, p.359, 1992 by R. G. Filippi and others). Further, it has been proved that EM in an aluminum alloy overlying a tungsten-plug depends upon the interconnection line length (see "Permitted Electromigration of Tungsten-plug Vias in Chain for Test Structure with Short Inter-plug Distance," Proc. of IEEE, VMIC, p.266, 1994 by T. Aoki and others). Furthermore, the fact that the EM depends upon the overlap margin (reservoir length) of aluminum interconnection line and tungsten-plug has been known to exist (see "An Electromigration Failure Model of Tungsten Plug Contacts/Vias for Realistic Lifetime Prediction, "VLSI Symp. p.192, 1996 by H. Kawasaki and C. K. Hu).
TABLE 1 LIFE ITEM (EM RESISTANCE) PARAMETERS SHORT LONG 1. CURRENT DENSITY HIGH LOW 2. LINE WIDTH ABOVE GRAIN BELOW GRAIN SIZE SIZE 3. CURRENT DIRECTION LINE.fwdarw.V i a V i a.fwdarw.LINE 4. LINE LENGTH LONG SHORT (BELOW 5 .mu.m) 5. CURRENT WAVEFORM DC DC PULSE AC 6. OVERLAP MARGIN SHORT LONG
Table 1 above is a list showing the foregoing parameters having affection on the electromigration, and the tendency of such affection. Integrating the foregoing prior art techniques, it is conceptually possible to incorporate the dependence of the electromigration upon the parameters shown in Table 1 into the foregoing Japanese patent applications. However, Incorporation of a single EM dependence parameter Into such a technique requires a process of verifying millions of interconnection lines. Further, providing corresponding tables to the parameters and verifying interconnection lines is enormously time-consuming and is impractical at all. Accordingly, these techniques have not been put into practical use yet. Practically, design rules allowing for conditions when the worst happens are applied to all interconnection lines. For example, in Japanese patent application pub. no.4-107953 which utilizes current values, an estimation of the maximum permissible current density at a point under worst condition Is formed. For example, if the maximum permissible electric current of an interconnection line having a width of 1 micrometer is determined at 1 milliampere, then it is determined such that an interconnection line having a width of 2 micrometers is formed at a point at which an electric current of 2 milliampere flows. Since maximum permissible current density needed at a point under the worst condition is applied to all locations, safety factor more than necessary is incorporated. As a result, although the miniaturization of individual semiconductor elements advances. it is difficult to achieve a reduction of the interconnection line dimensions therefore producing a bar to improving the level of semiconductor integrated circuit integration.